(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit such as that for use for a microprocessor or a memory device in which the operational timing is determined by a clock signal inputted externally thereof.
(2) Description of the Related Art
In this explanation, a microprocessor is taken as an example of a conventional semiconductor circuit. In recent years, the operational frequencies of internal clocks in microprocessors have dramatically increased and there are many examples in which such operational frequencies are in the order of 25 MHz. When considering further advancement in internal processing capability of the microprocessor, there is a barrier or neck in the capability with which the microprocessor will have access to and communicate data with a data source such as an external memory through an address bus or data bus. This barrier is called a "bus neck". Thus, in microprocessors having a high internal processing capability, a bus cycle with a minimum of two clocks for a cycle is often employed in order to reduce the problem of "bus neck" and for purposes of enhancing the efficiency in use of buses by reducing the time required for bus cycles.
On the other hand, with the reduction in the time required for one bus cycle, it becomes important to limit to small extent the delay time of an output signal such as an address signal or a bus cycle control signal of the microprocessor from a clock. For example, if a microprocessor having an internal clock frequency of 25 MHz executes one bus cycle within two clocks, the time required by the one bus cycle is only 80 nsec.
FIG. 1 is block diagram showing a conventional microprocessor. The microprocessor shown in FIG. 1 has an internal clock generating block 10 which includes a clock input buffer 12, a first clock driver 13, and a second clock driver 14. The clock input buffer 12 receives an external clock signal CLK from a clock input pad 11 and shapes its waveform. The first clock driver 13 receives an output from the clock input buffer 12 and generates a first internal clock CLK.sub.1 and a second internal clock CLK.sub.2 which are non-overlapping clocks. The clock driver 14 is identical in circuit construction to the clock driver 13. The clock driver 14 and the clock driver 13 are laid-out in a coupled pair and respectively generate the first internal clock CLK.sub.1 and the second internal clock CLK.sub.2 whose phases are non-overlapping. As shown in FIG. 1, the first internal clock CLK.sub.1 and the second internal clock CLK.sub.2 generated by the first clock input driver 13 and the second clock input driver 14 use in common a clock signal path for the first internal clock CLK.sub.1 and a clock signal path for the second internal clock CLK.sub.2, respectively.
An input/output control circuit 20 of the microprocessor produces a control signal OCS synchronous with the first internal clock CLK.sub.1, a latch control signal LTC for an output latch synchronous with the first internal clock CLK.sub.1, and an input mask signal IPM synchronous with the first internal clock CLK.sub.1. The latch control signal LTC is a signal which, in synchronization with the first internal clock CLK.sub.1 at the start of a data output bus cycle, becomes active (high) by one clock once for one data output bus cycle. The control signal OCS is a signal which, in synchronization with the first internal clock CLK.sub.1 before the start of the data output bus cycle, becomes active (high) once for one data output bus cycle and remains active until the timing of the first internal clock CLK.sub.1 at which the bus cycle is completed. A latch 21 receives the control signal OCS with the second internal clock CLK.sub.2 being applied as a latch signal and produces an output control signal OPC synchronous with the second internal clock CLK.sub.2. The input mask signal IPM becomes active (high) in synchronization with the first internal clock CLK.sub.1 when no data is inputted to the microprocessor.
The numeral 30 denotes a data input/output block for 1 bit in the microprocessor. The numeral 31 denotes a pad of a data input/output terminal. An input buffer 32 receives data inputted to the data input/output terminal pad 31 and an input latch 33 receives an output from the input buffer 32 with the second internal clock CLK.sub.2 being applied as a latch signal. The data latched by the input latch 33 at the timing of the second internal clock CLK.sub.2 is transferred to an input data register 40 via an internal signal path 41. At an output data register 50, the data outputted externally from the microprocessor is held at the timing synchronous with the first internal clock CLK.sub.1 and is inputted through an internal signal path 51 to an output latch 34 the output latch 34 receives the contents of the output data register 50 which have been transferred through the internal signal path 51, and is latch-controlled by the output latch control signal LTC with the second internal clock CLK.sub.2 being applied as a mask clock. An output three-state buffer 35 receives an output from the output latch 34 and outputs an output to the data input/output terminal pad 31 and is controlled for its output of an active state or an inactive state (high impedance state) by the output control signal OPC.
FIG. 2 is a timing chart for explaining the operation of the above conventional microprocessor. In FIG. 2, it is now assumed that two clocks of the microprocessor between the timing T.sub.60 and the timing T.sub.65 constitute a data output bus cycle. The timing specification values of the microprocessor are determined following those of external clock signal CLK. For example, a data output delay time is set as the time period from the rise of the external clock signal CLK (timing T.sub.61) to the settling of the data (timing T.sub.64). This data output delay time is thus the time period from the timing (timing T.sub.63) at which the output control signal OPC becomes active to the timing at which the output three-state buffer 35 completes the driving of the external load capacitance.
In the data output delay time from the timing of T.sub.61 to the timing of T.sub.64 in the conventional technique, there is included a delay time from the falling of the external clock signal CLK to the rising of the second internal clock CLK.sub.2, that is, the internal delay time (timing T.sub.61 to timing T.sub.62) of the internal clock generating block 10.
Generally, in a microprocessor constituted by CMOS transistors, the internal delay time of the internal clock generating block 10 is in the order of 5-10 nsec. As the operational frequency of the microprocessor becomes higher, there is a decrease in the bus cycle time as is noted above so that it is necessary to make the data output delay time shorter accordingly. If the microprocessor is of 25 MHz with 2 clock bus cycle, the internal delay time of 5-10 nsec is large and not negligible in the internal clock generating block 10 for 1 bus cycle of 80 nsec. Furthermore, if the operating temperature of the chip rises along with an upward change of the operational frequency of the microprocessor, there will be a further increase in the delay time due to an increase in an internal delay time of the internal clock generating block 10. This is a problem to be solved by the present invention, in the conventional semiconductor integrated circuit such as a microprocessor.